Goals

Course Goals and Objectives

Course Goals:

To provide students the ideas and concepts required to understand the architectures of modern microprocessors, including instruction set principles, instruction-level parallelism, memory hierarchy designs, and I/O; to provide students the analytical tools for assessing processor performance; and to provide students the opportunity to become familiar with the Internet and the technical literature as sources of current information on the topics of the course.

Course Objectives:

By the end of the course you should be able to ...

Describe analytical methods for measuring and reporting processor performance.
Apply Amdahl's law to determine the speedup of a processor resulting from processor enhancements.
Classify various instruction set architectures.
List and describe common processor addressing modes.
Discuss instruction set encoding and types of operands.
Describe the role of compilers in instruction set design.
Describe a basic processor pipeline.
List and discuss the various types of pipeline hazards.
Describe loop unrolling, scheduling, and forwarding as used for pipeline hazard elimination.
Describe techniques for static branch prediction.
Describe hardware techniques for dynamic branch prediction.
Describe a typical floating-point pipeline.
Describe the MIPS R4000 pipeline.
Define instruction-level parallelism (ILP).
List and discuss three types of instruction dependencies.
Describe dynamic scheduling as a technique for overcoming data hazards.
Describe dynamic scheduling with a scoreboard.
Describe the Tomasulo algorithm.
Discuss branch penalty reduction with dynamic hardware prediction.
Describe a simple superscalar architecture as a device for taking advantage of more ILP with multiple issue.
Discuss compiler support for exploiting more ILP.
Define conditional and predicated instructions.
Discuss compiler speculation and hardware speculation.
Describe the structure of the PowerPC 620.
Describe the memory hierarchy.
Discuss block placement, block identification, block replacement, and write policy as they apply to any level of the memory hierarchy.
Describe the concept of and basic structure of a cache.
Define direct mapped, associative, and set associative.
Describe the Alpha AXP 21064 data cache and instruction cache.
Discuss the analytical assessment of cache performance.
List and describe several techniques for reducing cache misses.
List and describe several techniques for reducing cache miss penalties.
List and describe several techniques for reducing cache hit time.
List and describe several techniques for improving main memory bandwidth.
List and discuss several differences between caches and virtual memory.
Discuss protection in virtual memory.
Describe protection in virtual memory.
Describe protection in the Intel Pentium and the Alpha AXP 21064.
Describe the Alpha AXP memory hierarchy.
Describe the S bus, Microchannel, PCI, IPI, and SCS1 2 I/O buses.
Describe several levels of RAID.

Taken from ABET Course Outline, updated Fall 1999 by Lane Branson